Electrostatic control of esd during PCB design - PCB manufacturing
From the PCB design to the protection of the static electricity on the mechanism, the plate is sealed in the outer casing with insulating material, no matter how much static electricity can be released.
With it, quickly let the static electricity lead to the main GND of the board, which can eliminate static electricity of a certain ability.
For non-metallic enclosures or products with metal backplanes, let me analyze the problem;
Focus on the internal circuit of the non-metallic enclosure and the ESD design of the PCB;
Refer to the following structure: (Note that some products contain metal backing inside)
For interference with PCBs that pass through the board:
(The electric field coupling and the magnetic field coupling are both grounded without a system!)
On the one hand, we have to plan the path of interference on the PCB (note that this is planned on the board-PCB layout); on the other hand, try to control the amplitude of the interference.
Note that some product housings are non-metallic; however, there is a metal backplane design for the strength of the product or for EMC design needs! We also pay attention to the following ESD paths;
Analyze: Why does the interference current cross the PCB?
It must be the interface and connection line on one side of the PCB circuit board. The input I/O interface and the connection line introduce interference, or the structure of the above products overlaps and holes! Interference from internal circuits, functional units, system traces to the earth! (System reference grounding plate) as shown in the two paths above!
In most cases, PCB PCBs have interfaces and connections that are common. If there are many interfaces and cables, there will be more difficulties in testing and rectification. No matter how complicated the system is, we still have countermeasures!
First plug and unplug the interface and cable one by one to see which interface or cable is unplugged to improve the immunity.
If you can find the connection line or interface that affects the immunity, we can directly bypass the clever use of the capacitor to bypass the interference! This is also a measure; I recommend the application in circuit design!
It is also one of the measures to reduce the interference current by placing a magnetic ring on the corresponding wire. (I use this method to guide customers to judge and analyze problems!)
If the plug-in interface or cable is not clearly discovered, planning the interference path will also avoid or reduce the interference current flowing through the sensitive circuit, such as avoiding interference current flowing through the CPU/MCU& control circuit and the crystal oscillator (oscillator layout!) Circuits, etc.
For the CPU/MCU, try to keep the pin in a high-impedance state and prevent interference current from flowing in!
CPU/MCU output pin, string resistor and bypass capacitor, do not pin the pin through the external circuit!
Even if there is no interference signal, the pin-through is unreasonable, which may cause damage to the CPU/MCU!
Reset analysis caused by ESD!
Note that a watchdog reset will also cause a software reset to reset!
The hardware reset is mainly two sources:
A. The power supply voltage is too low, and a reset signal is generated by the internal circuit of the CPU;
B. There is a reset pulse signal injection on the reset pin.
1. The CPU/MCU power cable is wired properly, and the decoupling capacitor is properly arranged. It is less likely to rely on the ESD coupling energy to pull the power supply to the reset level, which is not a priority.
2. There are more cases of interference on the reset pin, which is preferred.
(a) Whether the reset circuit leads are too long;
(b) Whether the reset circuit forms a large loop;
(c) Whether the chip reset pin is connected to a small capacitor to the nearest ground;
(d) Whether the reset signal is used by other chips;
(e) Is there a dedicated reset chip design, etc.;
A proper layout is not easy to generate a hard reset, which is relatively easy to handle compared to a restarter.
If it is a, b problem, it will also generate a reset in the radiation immunity test.
Close to the CPU reset pin to cut off the reset signal line string 1 ~ 10KΩ resistor, reset pin to the ground and 1 ~ 10nF capacitor. Relatively speaking, direct hard reset interference is still relatively easy to handle.
It is necessary to determine the system MCU/CPU-I/0 port or the control signal is disturbed and cause malfunction.
Since ESD is transient interference and the duration is very short, repeated reading of the control signal state can basically eliminate interference. Note that the added filter circuit may also be counterproductive; the exception: the combination of the bead and the capacitor will widen the interference level, and the signal confirmation time needs to be increased. For the program that needs fast response, it is necessary to consider it!
A. Determine the situation that an analog signal is disturbed due to interference; first judge by hardware.
Since ESD is transient interference, digital filtering programs can eliminate interference by eliminating the maximum and minimum values.
Similarly, the filter circuit will widen the interference signal, resulting in several intermittent interference signals, which cannot be completely eliminated.
B. The situation caused by interference causing a hard reset. There are two main situations that will cause the CPU/MCU to reset. One is that the reset pin is disturbed, and the other is that the voltage drop causes the power-on judgment circuit to generate a reset signal.
These are relatively easy to handle, and the addition of resistor-capacitor filtering and reasonable wiring can basically solve the problem.
C. It is more difficult to deal with the watchdog reset caused by a crash or crash.
It may be interference caused by any pin, which needs to be eliminated one by one. Since it is rarely introduced by a single pin, it is troublesome to handle. If there is no effective measure on the structure or peripheral circuit, the possibility of circuit board layout and re-routing Larger. The key problem of PCB: too large loop area causes problems!!
D. Software sensitivity, pin impedance Flash chip write operation; ESD pulse is short, the pulse train is not long, and does not necessarily overlap with the software sensitive state, so these conditions should be fully considered during test verification. Hardware design can improve the interference intensity, we must pay attention to the software sensitive links.
Mechanism Analysis of Circuit Board PCB Interference
1. Whether the metal component will produce an intersection dv/dt and be coupled to an adjacent sensitive circuit;
2. Verify that the discharge path is inductively coupled to the sensitive circuit due to parasitic inductance due to di/dt;
3. ESD usually has dv/dt and di/dt at the same time. Generally, dv/dt is more likely to generate coupling;
4. The common mode current pre-planning measures are not good, so that more common mode interference current flows through the sensitive circuit;
5. The sensitive circuit has a lower common mode impedance to ground, causing a larger common mode interference current to flow to the ground via the sensitive circuit.
The common mode interference current flowing through the sensitive circuit will not disappear, and it will also flow back to the ground. Any wire drawn from the sensitive circuit may be a way to flow the interference current flowing through the sensitive circuit back to the ground;
6. The common mode interference current will cause interference when the differential mode is generated in the sensitive circuit, and the sensitive circuit has a large impedance imbalance, so that the common mode interference current flowing through the differential mode voltage is generated;
7. The impedance of the interfered device is too high;
8. The device disturbed action threshold is too low;
9. The oscillator circuit works abnormally; the software is not able to separate and process the transient interference signal (or the software algorithm has a problem); for the electronic product or equipment whose system is a non-metallic enclosure; the electrostatic ESD contacts the bare metal part of the product At the same time, the discharge of the structure is very high voltage (>16KV) space discharge; there is a complex environment inside the system for electric field coupling and magnetic field coupling; the loop loop area is the key!!
We should focus on the routing of critical signal lines and the area of the loop; as explained below:
PCB and external electromagnetic field coupling
Magnetic field: u0=4Л*10^-7 Inductive voltage calculation: magnetic field & electric field
V=S× u0 ×ΔH/Δt
H=I/(2 × Л ×D )
V=S× E × FMHZ /48 frequency under electric field
Let me carry out the actual data calculation analysis: as explained below
A. Electric field problem! Parameter example description
è loop area = 20cm ^ 2 test field voltage is 30V / m @ 150MHZ, estimate the induced voltage?
B. Magnetic field problem! Field effect of ESD-electrostatic discharge
è loop area = 2cm^2 Distance from ESD test current (30A) = 50cm, Δt = 1ns
H=I/(2 ×Л ×D ) Estimated induced voltage?
Δt=1ns, H=I/(2×Л×D)=30/(2* Л *0.5)=10A/m
V=0.0002*4*Л*10^-7 * 10/(1*10^-9)
Conclusion: The loop area of the PCB with no grounding system corresponding to the strong interference environment is the key to the design!!
PCB PCB interference-ESD countermeasure analysis measures
A. Considering that dv/dt is the source, it can optimize the grounding performance of metal components to reduce dv/dt, increase the number of fasteners at the joint of metal components, increase the number of wires, shorten the length of the wire, and have some functions.
Test in 500V units to see if there is any change in the sensitive discharge voltage and conduct test analysis;
If there is a big improvement, the measures will be further increased until the experimental results are simulated.
B. Increasing the coupling distance and reducing the coupling capacitance to increase the coupling impedance, mainly compared to the wires close to the metal member and the PCB traces that are too close to the metal member. Confining the wire away from the metal components, inserting the Teflon sheet, inserting the independent shield protection, etc. can achieve some effects.
C. Analyze the path of the common mode interference current, increase the impedance of the sensitive line to the common mode interference current, and divert the common mode interference current to bypass the sensitive circuit. The actual measure is generally a string resistor and a capacitor. One end of the capacitor is generally connected to the nearest ground (there is also a better case of connecting to other places).
D. Increasing the common mode interference current of the sensitive circuit to the ground common mode impedance to reduce the shunt of the sensitive circuit.
Organize the interface cable to determine which ground impedance is low. In general, the power line to ground impedance is relatively low, and the magnetic ring is a way to increase the impedance. In the case of more interfaces and connecting lines, increasing the impedance of the power line is not necessarily effective or even counterproductive.
Repeat the magnetic loop on other control/detection connection lines (small current lines can be considered with resistors) to test the improvement. (This method is recommended for testing and improvement!)
The interference analysis of the key IC is affected by the specific chip pins!!
For example, there is a signal change on one of the pins of the known chip, causing the device to malfunction.
A. Strengthen the anti-jamming measures of this pin, close to the pin plus the bypass capacitor to the ground, and the string resistance is required when the interference source impedance is low;
B. Software filtering of the detection signal of the transient mutation.
C. Unblock the ground connection of each pin of the sensitive chip (or the incoming and outgoing lines of the circuit area), so that the interference current bypasses the chip (sensitive circuit). The main measure is to bypass the capacitor, which is beneficial to reduce the impedance of the pin to ground.
In the case where the impedance of the interference source is relatively low, the bypass capacitor is not effective, and the string resistance is good. This is a good and low-cost measure; pay attention to it when designing.
D. It is a more effective measure to select a chip with better anti-interference performance.
E. For more characteristic interference signals, especially narrow pulse interference signals, the software can be effectively eliminated and the cost is low.
The above measures are mutually exclusive and complementary, and effective and low-cost measures are selected to improve.
I am designing ESD in the actual circuit design of electronic products:
1. Avalanche diodes for ESD protection.
This is also a method often used in design. A typical approach is to connect an avalanche diode to the ground in a critical signal line. The method utilizes the ability of the avalanche diode to respond quickly and has stable clamping, which can consume the accumulated high voltage in a short period of time to protect the board.
2. Use high withstand voltage capacitors for circuit protection.
This approach typically places a high-withstand ceramic or Y-capacitor in the I/O connector or critical signal location, while the cable is as short as possible to reduce the inductive reactance of the cable. If a capacitor with low withstand voltage is used, it will cause damage to the capacitor and lose its protection.
3. Use ferrite beads for circuit protection.
Ferrite beads can attenuate ESD current well and also suppress radiation. When faced with two problems, a ferrite bead would be a good choice.
4. Spark gap method.
This method is seen in a material consisting of a layer of micro-belts made of copper, which is made up of triangular copper with pointed ends. The triangular copper is connected at one end to the signal line and the other is copper. Connected to the ground. When there is static electricity, a tip discharge is generated to consume electrical energy.
5. The protection circuit is implemented by the method of the LC filter.
The filter composed of LC can effectively reduce the high frequency static electricity entering the circuit.
The inductive reactance of the inductor is very good at suppressing the high-frequency ESD from entering the circuit, and the capacitor shunts the high-frequency energy of the ESD to the ground. At the same time, this type of filter can also round the edge of the signal with a small RF effect, and the performance aspect has further improved in signal integrity.
6, multi-layer board for ESD protection.
When the cost allows, the choice of multi-layer board is also a means to effectively prevent ESD. In multi-layer boards, ESD is more quickly coupled to the low-impedance plane due to a complete ground plane close to the traces, thus protecting the critical signals.
7, the method of protection of the protective tape around the periphery of the circuit board.
This method usually draws traces around the board without a solder layer. Connect the trace to the enclosure where possible, and note that the trace does not form a closed loop to avoid the trouble of forming a loop antenna.
8. Use CMOS devices with clamp diodes or TTL devices for circuit protection.
This method utilizes the principle of isolation for board protection. Because these devices are protected by clamp diodes, the design complexity is reduced in the actual circuit design.
9, the use of PCB decoupling capacitor design.
These decoupling capacitors have low ESL and ESR values. For low frequency ESD, the decoupling capacitor reduces the loop area. Due to the ESL effect, the electrolyte is weakened, which can better filter out high frequency energy. .
Let me summarize it; for electronic products/equipment-machine-level & board-level blocking and guiding
Plugging and guiding of the whole machine level system
1. Housing and mounting parts: Metal and conductive plating materials, etc., which are materials that are easy to attract and collect static electricity; ESD requires high-quality projects to avoid using these materials as much as possible.
2, must use the conductor material: the structure should be reserved in advance and the grounding point is evenly distributed; in general, the grounding effect of the thimble or metal dome is better than conductive foam and conductive cloth.
3, can not do the grounding treatment, such as plating side keys, etc., need to focus on the main board for special treatment;
(1) Add devices such as varistor, TVS or capacitor;
(2) reserve GND pin;
(3) The copper on the edge of the board attracts electrostatic discharge;
4. The metal parts on the outer casing must be more than 2.2mm away from the device and the trace.
5, on the stack to avoid the device exposed to the hole, seam edge; if it is unavoidable, it should be blocked in the assembly; common practice is to paste high temperature tape or anti-static tape and other barriers; all structural design needs to leave additional spacers Space.
Board level blocking and guiding
1. Increase the PCB board area to increase the GND area and enhance the ability to neutralize static electricity; cost or differentiated stacks allow us to make small.
2. For a very small board, you must have at least one complete GND layer; and be able to maintain a good connection with the battery feet; we often leave a complete formation because of the cost.
3, a small circuit board, because the board's neutralization charge capacity is limited, it is necessary to consider blocking from the whole machine, less consideration.
4. For device selection, devices with high withstand voltage ESD should be selected; when the electrostatic protection device is selected, its capacitance should be considered to avoid the failure of the signal itself.
5. When the device is placed, the device that is easily affected by ESD should be covered in the shield as much as possible.
6. The shield must ensure an effective and evenly distributed grounding! It should be directly connected to the main ground, and the blind holes should be directly combined with the buried holes;
7. For some circuits that are easily exposed, such as IO ports and keyboards, electrostatic protection devices must be added.
8, the device placed, must comply with the principle of near release, ESD protection device should be placed close to the IO and side keys; secondly, across the middle of the road; avoid close to the chip placement; this can reduce the ESD pulse signal into the nearby line Transient coupling; although there is no direct connection, this secondary radiation effect can also disrupt other parts of the work.
9, Layout routing must adhere to the principle of effective protection; the line should go from the interface to the TVS first, and then go to the CPU and other chips; far away from the electrostatic protection device on the signal line, because Excessive parasitic inductance of the lead leads to protection failure, making the protection virtually useless.
10. The connection between the grounding leg of the TVS tube and the main ground must be as short as possible to reduce the parasitic inductance of the ground plane.
11. TVS devices should be placed as close as possible to the connector to reduce transient coupling into nearby lines. Although there is no direct path to the connector, this secondary radiation effect can also cause malfunctions in other parts of the board.
12. Avoid important signal lines on the board side; for example, clock and reset signals.
13. The unused area on the main board is paved as much as possible; and connected to the main ground; multi-flooring reduces the distance between the signal and the ground, which is equivalent to reducing the loop area of the signal. (The larger the area, the larger the field flow involved and the higher the induced current)
14. It is important to note that ESD's direct discharge to the formation may damage sensitive circuits. One or more high frequency bypass capacitors are also used while using the TVS diodes, which are placed between the power supply of the consumable component and ground. The bypass capacitor reduces charge injection and maintains the voltage difference between the power supply and the ground port.
15. The PCB design power supply is better in the middle of the motherboard than on the board side; the ground layout is better in the middle of the board than the board side.
We have carried out the above analysis and summary through a number of practical projects; the ESD problem will not exceed our summary!
If you understand and understand our analysis and pcb design ideas for the system, you can save a lot of money for your product design and development!
The above content is provided by PCB design engineer (Juding Circuit Technology), please consult the staff for more details!
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