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High-frequency signal PCB circuit board, PCB design difficulties

2019-09-10 21:21:26 442

     If the high-frequency model PCB design can be as simple as connecting the schematic nodes and as beautiful as seen on a computer monitor, that would be a wonderful thing. However, unless you are new to engineer PCB design, or are very fortunate, the actual PCB design is usually not as simple as the circuit design they are engaged in. PCB design engineers face many new challenges before the PCB design finally works and some people affirm the PCB performance. This is the current status of high frequency board PCB design.


Design rules and design guidelines are constantly evolving, and if they are lucky, they will form a successful solution.


     Most PCB design engineers are proficient in the working principle and interaction of PCB devices and the various data transmission standards that make up the input and output of the board. The schematic designer may know a little, and may not even know the principle. What happens when the graph is converted to a printed circuit copper wire. The results of mutual cooperation between professional layout PCB design engineers. Often, the master of the board is responsible for the success or failure of the final board. However, the more schematic PCB design engineers know about good layout techniques, the more opportunities there are to avoid major problems.


     If the PCB design contains a high-density FPGA, there are likely to be many challenges placed in front of a well-designed schematic. Including hundreds of input and output ports, operating frequencies exceeding 500MHz (which may be higher in some designs), and solder ball pitches as small as half a millimeter, etc., all of which will result in undue design units The mutual influence.


PCB design concurrent switching noise

      The first challenge is probably the so-called concurrent switching noise (SSN) or concurrent switching output (SSO). A large amount of high-frequency data streams will cause problems such as ringing and crosstalk on the data lines, and ground bounce and power supply noise problems that affect the performance of the entire board on the power board and ground plane.


      In order to solve ringing and crosstalk on high frequency data lines, switching to differential signals is a good first step. Since one line on the differential pair is the sink terminal and the other provides the source current, the inductive effect can be fundamentally eliminated. When data is transmitted using a differential pair, it helps to reduce the "bounce" noise generated by the induced current in the return path since the current remains locally. For RF up to hundreds of MHz or even several GHz, the signal theory shows that the maximum signal power can be transmitted during impedance matching.


       When the transmission line is not well matched, a reflection will occur, and only a part of the signal will be transmitted from the originating end to the receiving device, while other parts will bounce back and forth between the transmitting end and the receiving end. The quality of the differential signal on the PCB will play a large role in impedance matching (and other aspects).


Differential trace PCB design

      The differential trace design is based on the principle of impedance controlled PCB. The model is a bit like a coaxial cable. On an impedance controlled PCB, the metal planar layer can be used as a shield, the insulator is an FR4 laminate, and the conductor is a signal trace pair. The average dielectric constant of FR4 is between 4.2 and 4.5. Since the manufacturing error is not known, it may cause excessive etching of the copper wire, eventually causing an impedance error. The most accurate way to calculate the trace impedance of a PCB is to use a field parsing program (usually two-dimensional, sometimes three-dimensional), which requires the use of finite elements to directly solve Maxwell's equations for the entire PCB batch. The software analyzes EMI effects based on trace spacing, line width, line thickness, and the height of the insulation.


The 100Ω characteristic impedance has become the industry standard for differential connections. A 100Ω differential line can be made with two 50Ω single-ended lines of equal length. Since the two traces are close to each other, the field coupling between the lines will reduce the differential mode impedance of the line. In order to maintain the impedance of 100Ω, the width of the trace must be reduced a little. As a result, the common mode impedance of each of the 100Ω differential pairs will be slightly higher than 50 ohms.


Theoretically, the size of the traces and the materials used determine the impedance, but vias, connectors, and even device pads introduce impedance discontinuities in the signal path. It is usually impossible to use these things. Sometimes, for more reasonable layout and routing, you need to increase the number of layers of the PCB, or add functions like buried holes.


The buried via only connects part of the PCB, but it also increases the manufacturing cost of the board while solving the problem of the transmission line. But sometimes there is no choice at all. As signal speeds get faster and space gets smaller, additional demands such as buried vias begin to increase, which should be a cost factor for PCB solutions.


The cross section is the most common pattern of actual differential line layouts. When stripline wiring is used, the signal is sandwiched by the FR-4 material.


In the case of a microstrip line, a conductor is exposed to the air. Because air has the lowest dielectric constant (Er = 1), the top layer is best suited for routing critical signals such as clock signals or high frequency SERial-DESerial (SERDES) signals.


The microstrip line wiring should be coupled to a ground plane that reduces electromagnetic interference (EMI) by absorbing a portion of the electromagnetic field lines. In the stripline, all of the electromagnetic field lines are coupled to the upper and lower reference planes, which greatly reduces EMI.


If possible, try not to use a wide-edge coupled stripline design. This structure is susceptible to the differential noise coupled in the reference plane. There is also a need for balanced manufacturing of PCBs, which is difficult to control. In general, it is relatively easy to control the line spacing on the same layer.


Decoupling and bypass capacitors

      Another important aspect of determining whether the actual performance of the PCB meets expectations is to increase control by adding decoupling and bypass capacitors. Adding decoupling capacitors helps reduce the inductance between the PCB's power supply and ground plane and helps control the signal and IC impedance across the PCB. The bypass capacitor helps provide a clean power supply to the FPGA (providing a charge bank). The traditional rule is to place decoupling capacitors anywhere convenient for PCB layout, and the number of FPGA power pins determines the number of decoupling capacitors. However, the ultra-high switching speed of FPGAs completely breaks this stereotype.


In a typical FPGA board design, the capacitor closest to the power supply provides frequency compensation for the current change of the load. To provide low frequency filtering and prevent the supply voltage from dropping, use large decoupling capacitors. The voltage drop is due to the lag of the regulator's response when the design circuit starts. This large capacitance is usually an electrolytic capacitor with a good low frequency response, and its frequency response ranges from DC to several hundred kHz.


      Each FPGA output change requires charging and discharging the signal line, which requires energy. The function of the bypass capacitor is to provide local energy storage over a wide frequency range. In addition, small capacitors with small series inductance are required to provide high-speed current for high-frequency transients. The large capacitor with slow response continues to supply current after the high frequency capacitor energy is consumed.


The large number of current transients on the power bus increases the complexity of the FPGA design. This current transient is usually associated with SSO/SSN. Capacitors with very small inductors will provide local high frequency energy that can be used to eliminate switching current noise on the power bus. This decoupling capacitor that prevents high frequency current from entering the device supply must be very close to the FPGA (less than 1 cm). Many small capacitors are sometimes connected in parallel as a local energy storage for the device and respond quickly to changes in current demand.


In general, the wiring of the decoupling capacitors should be absolutely short, including the vertical distance in the vias. Even adding a little bit increases the inductance of the wire, which reduces the effect of decoupling.


Other technical solutions

As signal speeds increase, it becomes increasingly difficult to easily transfer data on a board. Other techniques can be utilized to further enhance the performance of the PCB.


The first and most obvious method is the simple device layout. It is common sense to design the shortest and most direct path for the most critical connections, but don't underestimate this. Since the simplest strategy can get the best results, why bother to adjust the signal on the board?


Almost the same simple method is to consider the width of the signal line. When the data rate is as high as 622MHz or higher, the skin effect of signal conduction becomes more and more prominent. When the distance is long, very thin traces on the PCB (such as 4 or 5 mils) will cause a large attenuation of the signal, just like an undesigned low-pass filter with attenuation, with attenuation The frequency increases and increases. The longer the backplane, the higher the frequency and the wider the width of the signal line. For backplane traces longer than 20 inches, the line width should be 10 or 12 mils.


Usually, the most critical signal on the board is the clock signal. When the clock line PCB is designed to be too long or not good, the jitter and offset will be amplified downstream, especially when the speed is increased. Multiple layers should be avoided to transfer clocks, and there should be no vias on the clock line because the vias will increase impedance variations and reflections. If the inner layer must be used to route the clock, the upper and lower layers should use the ground plane to reduce the delay.


When the design uses an FPGAPLL, noise on the power plane increases PLL jitter. If this is critical, a “power island” can be created for the PLL that uses a thicker etch in the metal plane to isolate the PLL analog and digital supplies.


For signals that exceed 2 Gbps, a more costly solution must be considered. At such high frequencies, backplane thickness and via design have a large impact on signal integrity. The effect is better when the thickness of the backing plate does not exceed 0.200 inches.


When the high-speed signal on the PCB, the number of layers should be as small as possible, which can limit the number of vias. In thick plates, the vias that connect the signal layers are long and will form a transmission line branch on the signal path. The use of buried holes can solve this problem, but the manufacturing cost is high.


Another option is to use low-loss dielectric materials such as Rogers 4350, GETEK or ARLON. These materials may nearly double the cost of FR4 materials, but sometimes this is the only option.


There are other design techniques for FPGAs that offer some choice of I/O locations. In critical high-speed SERDES designs, SERDESI/O can be isolated by leaving (but not using) adjacent I/O pins.


For example, a 3x3 or 5x5 BGA sphere region may be reserved relative to SERDESRx and Tx, VCCRX# and VCCTX#, and ball position. Or, if possible, keep the entire I/O group close to the SERDES. If there are no I/O limitations in the design, these technologies can bring benefits without increasing costs.


     Finally, one of the best methods is to refer to the reference board provided by the FPGA manufacturer. Most manufacturers will provide source layout information for the reference board, although special requests may be required due to private information issues.


These boards typically contain standard high-speed I/O interfaces that are required by FPGA manufacturers to characterize and authenticate their devices.


Keep in mind, however, that these boards are often designed for a variety of uses and do not necessarily match the specific design requirements. Even so, they can still serve as a starting point for creating solutions.


      Of course, this article only talks about some basic concepts. The key is to figure out what the goal is before investing a lot of time and effort into the PCB board schematic design. Once the schematic design is complete, redesigning can take a lot of time and money, even with a slight adjustment to the width of the trace. You can't rely on PCB schematic engineers to make PCB designs that meet your actual needs. Schematic design engineers must always provide guidance, make savvy choices, and take responsibility for the success of the solution.


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