Analysis of layout and routing methods for mixed-signal PCB design

2019-09-27 19:26:25

The operation of analog circuits relies on continuously varying currents and voltages. The operation of the digital circuit relies on the detection of a high or low level at the receiving end based on a predefined voltage level or threshold, which is equivalent to determining the "true" or "false" of the logic state.

Between the high and low levels of the digital circuit, there is a "gray" area in which digital circuits sometimes exhibit analog effects, such as when transitioning from low to high (state), if digital The speed of the jump is fast enough to produce overshoot and ringback reflections. For modern board designs, the concept of mixed-signal PCBs is ambiguous because analog circuits and analog effects exist even in purely "digital" devices.

Therefore, in the early stages of design, in order to reliably achieve strict timing assignment, simulation effects must be simulated. In fact, in addition to the reliability of communication products that must last for years without problems, simulations of simulation effects are particularly needed in mass-produced low-cost/high-performance consumer products. (Juding Circuit Technology, you provide articles.)

Another difficulty in modern mixed-signal PCB design is the increasing number of devices with different digital logic, such as GTL, LVTTL, LVCMOS, and LVDS logic. The logic threshold and voltage swing of each logic circuit are different, but these different logic thresholds The circuit with the voltage swing must be designed together on a PCB. Here, you can master successful strategies and techniques by thoroughly analyzing the layout and layout of high-density, high-performance, mixed-signal PCBs.

Mixed signal circuit wiring basis

When digital and analog circuits share the same components on the same board, the layout and routing of the circuit must be methodical.

In mixed-signal PCB designs, there are special requirements for power traces and the isolation of analog noise and digital circuit noise is required to avoid noise coupling, which increases the complexity of layout and routing. The special requirements for power transmission lines and the need to isolate noise coupling between analog and digital circuits further increase the complexity of the layout and routing of mixed-signal PCBs.

If the power supply of the analog amplifier in the A/D converter and the digital power supply of the A/D converter are connected together, it is highly likely that the interaction between the analog part and the digital part circuit will occur. Perhaps, due to the location of the input/output connectors, the layout scheme must mix the wiring of the digital and analog circuits.

Before laying out and routing, engineers need to figure out the basic weaknesses of layout and routing solutions. Even with false judgments, most engineers tend to use layout and routing information to identify potential electrical effects.

Layout and routing of modern mixed-signal PCBs

The following is a description of the hybrid signal PCB layout and routing techniques through the design of the OC48 interface card. OC48 stands for Optical Carrier Standard 48, which is basically oriented to 2.5Gb serial optical communication. It is one of the high-capacity optical communication standards in modern communication equipment. The OC48 interface card contains layout and routing issues for several typical mixed-signal PCBs, and the placement and routing process will indicate the order and steps to resolve the mixed-signal PCB layout scheme.

The OC48 card contains an optical transceiver that converts optical signals and analog electrical signals in both directions. Analog signal input or output digital signal processor, which converts these analog signals to digital logic levels for connection to microprocessors, programmable gate arrays, and system interface circuits for DSPs and microprocessors on OC48 cards . Independent phase-locked loops, mains filters and local reference voltage sources are also integrated.

Among them, the microprocessor is a multi-power device, the main power is 2V, and the 3.3V I/O signal power is shared by other digital devices on the board. The independent digital clock source clocks the OC48I/O, the microprocessor, and the system I/O.

After checking the layout and wiring requirements of different functional circuit blocks, it is initially recommended to use a 12-layer board. The configuration of the microstrip and stripline layers can safely reduce the coupling of adjacent trace layers and improve impedance control.

A ground plane between the first and second layers isolates the wiring of the sensitive analog reference source, CPU core, and PLL filter power supply from the microprocessor and DSP devices on the first level. The power and ground planes are always in pairs, as is done on the OC48 card for sharing the 3.3V power plane. This will reduce the impedance between the power supply and ground, thereby reducing noise on the power supply signal.

Avoid walking the digital clock line and high-frequency analog signal lines near the power plane. Otherwise, the noise of the power signal will be coupled into the sensitive analog signal.

Careful consideration should be given to the use of power and analog ground plane splices, especially at the input and output of mixed-signal devices, depending on the needs of the digital signal routing. Passing an open trace around the signal layer can result in impedance discontinuities and poor transmission line loops. These can cause signal quality, timing and EMI issues.

Sometimes a number of ground planes are added, or a number of peripheral layers are used for a local power plane or ground plane underneath a device to eliminate the opening and avoid the above problems. Multiple ground planes are used on the OC48 interface card. Maintaining the layered symmetry of the position of the opening layer and the wiring layer can avoid card deformation and simplify the manufacturing process. Due to the high current resistance of the 1 oz CCL, the 1 oz CCL is used for the 3.3V power plane and the corresponding ground plane, and the 0.5 oz CCL for the other layers, which can reduce the transient high current or spike period. Voltage fluctuations.

If you are designing a complex system from the ground plane, a 0.093-inch and 0.100-inch thickness card should be used to support the wiring layer and the ground isolation layer. The thickness of the card must also be adjusted according to the wiring features of the via pads and holes so that the aspect ratio of the drilled diameter to the finished card thickness does not exceed the aspect ratio of the metallized holes provided by the manufacturer.

If you want to design a low-cost, high-volume commercial product with a minimum number of routing layers, carefully consider the wiring details of all the special power supplies on the mixed-signal PCB before laying out or routing. Before starting the layout and routing, let the target manufacturer review the initial stratification plan. Basically, depending on the thickness of the finished product, the number of layers, the weight of the copper, the impedance (with tolerance), and the minimum size of the via pads and holes, the manufacturer should provide stratification recommendations in writing.

A configuration example of all controlled impedance striplines and microstrip lines is included in the recommendations. To combine your predictions of impedance with the manufacturer's impedance, then use these impedance predictions to verify the signal routing characteristics of the simulation tools used to develop CAD routing rules.

OC48 card layout

The high speed analog signal between the optical transceiver and the DSP is very sensitive to external noise. Similarly, all special power and reference voltage circuits also create a large amount of coupling between the card's analog and digital power transfer circuits. Sometimes, due to the shape of the casing, high-density boards have to be designed. Due to the orientation of the external cable access card and the high component size of the optical transceiver, the position of the transceiver in the card is largely fixed. The system I/O connector position and signal assignment are also fixed. This is the basic work that must be done before the layout.

As with most successful high-density analog layout and routing schemes, the layout must meet the wiring requirements, and the layout and routing requirements must be balanced. For the analog part of a mixed-signal PCB and the local CPU core with a 2V operating voltage, the “first layout and post-route” method is not recommended. For the OC48 card, the portion of the DSP analog circuit that contains the analog reference voltage and the analog supply bypass capacitor should be interconnected first. After the wiring is completed, the entire DSP with analog components and wiring is placed close enough to the optical transceiver to ensure that the high-speed analog differential signal to the DSP has the shortest wiring length, minimum bend and via. The symmetry of the differential layout and routing will reduce the effects of common mode noise. However, it is difficult to predict the best solution for layout before wiring.

Consult the chip distributor for the design guidelines for the PCB board. Communicate with the application engineer of the distributor before designing according to the guidelines. Many chip distributors have strict time limits for providing high quality layout recommendations. Sometimes, the solutions they offer are viable for "first-tier customers" who use the device. In the area of signal integrity (SI) design, the signal integrity design of new devices is particularly important. OC48 card layout with integrated DSP and microprocessor can be started according to the distributor's basic guidelines and the specific requirements of each power and ground pin in the package.

After the position and wiring of the high frequency analog section are determined, the remaining digital circuits can be placed in the grouping method shown in the block diagram. Care should be taken to carefully design the following circuits: the location of the PLL power supply filter circuit in the CPU with high sensitivity to the analog signal; the local CPU core voltage regulator; the reference voltage circuit for the "digital" microprocessor.

The electrical and manufacturing guidelines for digital cabling are now properly applied to the design. The aforementioned design of signal integrity for high speed digital buses and clock signals reveals some special wiring topology requirements for time-delay matching of processor bus, balanced Ts, and certain clock signal routing. But you may not know, there are also suggestions for updating, that is, adding a number of termination resistors.

In the process of solving the problem, it is a matter of course to make some adjustments in the layout stage. However, before starting the routing, an important step is to verify the timing of the digital portion according to the layout scheme. At this point, a full DFM/DFT layout review of the board will help ensure that the card meets the customer's needs.

Digital wiring for OC48 card

For the digital portion of the digital device power line and mixed-signal DSP, digital routing begins with the SMD wayout. Use the shortest and widest traces allowed by the assembly process. For high-frequency devices, the trace of the power supply is equivalent to a small inductor that will degrade the power supply noise and create undesirable coupling between the analog and digital circuits. The longer the power trace, the larger the inductance.

Optimal layout and routing schemes are available with digital bypass capacitors. In short, the location of the bypass capacitors is fine-tuned as needed to make it easy to install and distribute around the digital components and the digital portion of the mixed-signal device. The bypass capacitor routing diagram is routed using the same "shortest and widest trace" method.

When the power branch is going through a continuous plane (such as the 3.3V power plane on the OC48 interface card), the power supply pins and the bypass capacitors themselves do not have to share the same exit pattern to get the lowest inductance and ESR bypass. On a mixed-signal PCB such as an OC48 interface card, pay special attention to the wiring of the power branch. Remember to place additional bypass capacitors in a matrix arrangement on the entire card, even if placed near passive components.

Once the power outlet map is determined, you can begin automatic routing. The ATE test contacts on the OC48 card are defined during logic design. Make sure that ATE is exposed to 100% of the nodes. In order to implement an ATE test with a minimum ATE test probe of 0.070 inches, the position of the breakout via must be preserved to ensure that the power plane is not interrupted by the intersection of the vias of the vias.

If a power and ground plane split scheme is to be used, the layer bias should be selected on adjacent wiring layers parallel to the opening. The prohibition of the wiring area is defined by the circumference of the opening area on the adjacent layer to prevent the wiring from entering. If the wiring must pass through the open area to another layer, make sure that the other layer adjacent to the wiring is a continuous ground plane. This will reduce the reflection path. Having the bypass capacitor across the open power plane is good for some digital signal layouts, but bridging between digital and analog power planes is not recommended because the noise is coupled to each other through the bypass capacitor.

Several of the latest auto-routing applications are capable of routing high-density multi-layer digital circuits. In the initial wiring phase, use a 0.050 inch large via pitch in the SMD exit and consider the type of package used. The subsequent routing stages should allow the vias to be placed close to each other so that all tools can achieve the highest throughput. And the lowest number of vias. Since the OC48 processor bus uses an improved star topology, it has the highest priority in automatic routing.

to sum up

Signal integrity verification and timing simulation are performed after the OC48 card board is completed. The simulation proves that the wiring guidance meets the expected requirements and improves the timing specifications of the second layer bus. At the end of the design rule check, final manufacturing review, mask and review and issued to the manufacturer, the layout task is officially ended.

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